Here is a very nice project that [Znaxque] finished a few months ago: a simple nixie clock made with logic gates only. In this build, the mains 50Hz is used as a time base instead of a 32KHz ...

Also it provide the necessary pull/push information for clock logic while clock tree building. Clock Gate Aware Design Closure Algorithm follows: Based on the load on clock gating cells their negative ...

Asynchronous logic - yes or no?? This will probably be the wrong question in the future.As clock rates and gate counts increase to achieve more functionality, designers of mobile consumer products ...